SH-2A Datasheet, PDF (187/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.4.10 BSRF
Branch to SubRoutine Far
Branch to Subroutine Procedure
Branch Instruction
Delayed Branch Instruction
Format
BSRF Rm
Abstract
PC → PR, Rm + PC → PC
Code
Cycle T Bit
0000mmmm00000011 2
—
Description
Branches to the subroutine procedure at a specified address after executing the instruction
following this BSRF instruction. The PC value is stored in the PR. The branch destination is PC +
the 32-bit contents of the general register Rm. However, in this case it is used for address
calculation. The PC is the address 4 bytes after this instruction. Used as a subroutine procedure
call in combination with RTS.
Note
Since this is a delayed branch instruction, the instruction after BSR is executed before branching.
No interrupts and address errors are accepted between this instruction and the next instruction. If
the next instruction is a branch instruction, it is acknowledged as an illegal slot instruction.
Operation
BSRF(long m) /* BSRF Rm */
{
PR=PC
PC=PC+R[m];
Delay_Slot(PR+2);
}
Rev. 3.00 Jul 08, 2005 page 173 of 484
REJ09B0051-0300