SH-2A Datasheet, PDF (62/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 5 Instruction Set
Classification
Arithmetic
operation
instructions
Instruction
Type
Op Code
26
ADD
ADDC
ADDV
CMP/cond
CLIPS
CLIPU
DIVS
DIVU
DIV1
DIV0S
DIV0U
DMULS
DMULU
DT
EXTS
EXTU
MAC
MUL
MULR
MULS
MULU
NEG
NEGC
SUB
SUBC
SUBV
Function
Number of
Instructions
Binary addition
40
Binary addition with carry
Binary addition with overflow
Comparison
Signed saturation value comparison
Unsigned saturation value comparison
Signed division (32 ÷ 32)
Unsigned division (32 ÷ 32)
1-step division
Signed 1-step division initialization
Unsigned 1-step division initialization
Signed double-precision multiplication
Unsigned double-precision
multiplication
Decrement and test
Sign extension
Zero extension
Multiply and accumulate, double-
precision multiply and accumulate
Double-precision multiplication
Rn result storage signed multiplication
Signed multiplication
Unsigned multiplication
Sign inversion
Sign inversion with borrow
Binary subtraction
Binary subtraction with borrow
Binary subtraction with underflow
Rev. 3.00 Jul 08, 2005 page 48 of 484
REJ09B0051-0300