SH-2A Datasheet, PDF (75/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 5 Instruction Set
5.1.3 Logic Operation Instructions
Table 5.5 Logic Operation Instructions
Instruction
AND Rm, Rn
AND #imm, R0
AND.B #imm, @(R0, GBR)
NOT Rm, Rn
OR Rm, Rn
OR #imm, R0
OR.B #imm, @(R0, GBR)
TAS.B @Rn
TST Rm, Rn
TST #imm, R0
TST.B #imm, @(R0, GBR)
XOR Rm, Rn
XOR #imm, R0
XOR.B #imm, @(R0, GBR)
Code
Operation
Cycles T Bit
0010nnnnmmmm1001 Rn & Rm → Rn
11001001iiiiiiii R0 & imm → R0
11001101iiiiiiii (R0+GBR) & imm
→ (R0+GBR)
0110nnnnmmmm0111 ~ Rm → Rn
0010nnnnmmmm1011 Rn | Rm → Rn
11001011iiiiiiii R0 | imm → R0
11001111iiiiiiii (R0+GBR) | imm → (R0+GBR)
0100nnnn00011011 When (Rn) = 0, 1→T,
otherwise 0 → T,
1 → MSB of (Rn)
0010nnnnmmmm1000 Rn & Rm; when result = 0,
1 → T, otherwise 0 → T
11001000iiiiiiii R0 & imm; when result = 0,
1 → T, otherwise 0 → T
11001100iiiiiiii (R0 + GBR) & imm;
when result = 0, 1 → T,
otherwise 0 → T
0010nnnnmmmm1010 Rn ^ Rm → Rn
11001010iiiiiiii R0 ^ imm → R0
11001110iiiiiiii (R0+GBR) ^ imm →
(R0+GBR)
1
―
1
―
3
―
1
―
1
―
1
―
3
―
3 Test
result
1 Test
result
1 Test
result
3 Test
result
1
―
1
―
3
―
Compatibility
SH2E
SH4
New
SH-2A/
SH2A-
FPU
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Rev. 3.00 Jul 08, 2005 page 61 of 484
REJ09B0051-0300