SH-2A Datasheet, PDF (249/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.4.40 NEGC
NEGate with Carry
Sign Inversion with Borrow
Section 6 Instruction Descriptions
Arithmetic Instruction
Format
NEGC Rm,Rn
Abstract
0 – Rm – T → Rn, Borrow → T
Code
Cycle T Bit
0110nnnnmmmm1010 1
Borrow
Description
Subtracts general register Rm data and the T bit from 0, and stores the result in Rn. If a borrow is
generated, T bit changes accordingly. This instruction is used for inverting the sign of a value that
has more than 32 bits.
Operation
NEGC(long m,long n) /* NEGC Rm,Rn */
{
unsigned long temp;
temp=0-R[m];
R[n]=temp-T;
if (0<temp) T=1;
else T=0;
if (temp<R[n]) T=1;
PC+=2;
}
Examples:
CLRT
NEGC R1,R1
NEGC R0,R0
; Sign inversion of R1 and R0 (64 bits)
; Before execution: R1 = H'00000001, T = 0
; After execution: R1 = H'FFFFFFFF, T = 1
; Before execution: R0 = H'00000000, T = 1
; After execution: R0 = H'FFFFFFFF, T = 1
Rev. 3.00 Jul 08, 2005 page 235 of 484
REJ09B0051-0300