SH-2A Datasheet, PDF (405/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

CLIP.B Rn
CLIP.W Rn
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ Slots
IF ID EX
IF ID EX ⋅ ⋅ ⋅
IF ID EX ⋅ ⋅ ⋅
Section 8 Pipeline Operation
Operation
The pipeline ends after three stages: IF, ID, EX. In the EX stage, the data operation is completed
via the ALU.
Instruction Issuance
The EXTS.B, EXTS.W, EXTU.B, and EXTU.W instructions use the shifter.
The other instructions do not cause resource contention.
Parallel Execution Capability
With CLIP instructions, CS bit rewrite contention does not occur and parallel execution is
possible.
Rev. 3.00 Jul 08, 2005 page 391 of 484
REJ09B0051-0300