SH-2A Datasheet, PDF (289/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.4.68
XTRCT
Middle Extraction
from Linked Registers
eXTRaCT
Format
Abstract
XTRCT Rm,Rn Rm: Center 32 bits of Rn → Rn
Section 6 Instruction Descriptions
Data Transfer Instruction
Code
Cycle T Bit
0010nnnnmmmm1101 1
—
Description
Extracts the middle 32 bits from the 64 bits of coupled general registers Rm and Rn, and stores the
32 bits in Rn (figure 6.13).
MSB
Rm
LSB MSB
LSB
Rn
Rn
Figure 6.13 Extract
Operation
XTRCT(long m,long n) /* XTRCT Rm,Rn */
{
unsigned long temp;
temp=(R[m]<<16)&0xFFFF0000;
R[n]=(R[n]>>16)&0x0000FFFF;
R[n]|=temp;
PC+=2;
}
Example:
XTRCT R0,R1 ; Before execution:
; After execution:
R0 = H'01234567, R1 = H'89ABCDEF
R1 = H'456789AB
Rev. 3.00 Jul 08, 2005 page 275 of 484
REJ09B0051-0300