SH-2A Datasheet, PDF (171/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.4 SH-2E CPU Instructions
6.4.1
ADD
Binary Addition
ADD Binary
Arithmetic Instruction
Format
ADD Rm,Rn
ADD #imm,Rn
Abstract
Rm + Rn → Rn
Rn + imm → Rn
Code
0011nnnnmmmm1100
0111nnnniiiiiiii
Cycle
1
1
T Bit
—
—
Description
Adds general register Rn data to Rm data, and stores the result in Rn. 8-bit immediate data can be
added instead of Rm data. Since the 8-bit immediate data is sign-extended to 32 bits, this
instruction can add and subtract immediate data.
Operation
ADD(long m,long n) /* ADD Rm,Rn */
{
R[n]+=R[m];
PC+=2;
}
ADDI(long i,long n) /* ADD #imm,Rn */
{
if ((i&0x80)==0) R[n]+=(0x000000FF & (long)i);
else R[n]+=(0xFFFFFF00 | (long)i);
PC+=2;
}
Examples:
ADD R0,R1
ADD #H'01,R2
ADD #H'FE,R3
; Before execution:
; After execution:
; Before execution:
; After execution:
; Before execution:
; After execution:
R0 = H'7FFFFFFF, R1 = H'00000001
R1 = H'80000000
R2 = H'00000000
R2 = H'00000001
R3 = H'00000001
R3 = H'FFFFFFFF
Rev. 3.00 Jul 08, 2005 page 157 of 484
REJ09B0051-0300