SH-2A Datasheet, PDF (102/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.3 New Instructions
6.3.1
BAND
Bit AND
Bit Logical AND
Bit Manipulation Instruction
SH-2A/SH2A-FPU (New)
Format
Abstract
Code
Cycle T Bit
BAND.B #imm3, @(disp12,Rn) (<imm> of (disp+Rn)) & T 0011nnnn0iii10010100dddddddddddd 3
→T
Operation
result
Description
ANDs a specified bit in memory at the address indicated by (disp + Rn) with the T bit, and stores
the result in the T bit. The bit number is specified by 3-bit immediate data. With this instruction,
data is read from memory as a byte unit.
BAND.B #imm3, @(disp12, Rn)
Specified by #imm3
7
0
(disp+Rn)
T
&
T
Rev. 3.00 Jul 08, 2005 page 88 of 484
REJ09B0051-0300