SH-2A Datasheet, PDF (350/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
Instructions that perform FPU arithmetic operations use the FPU arithmetic operation pipeline.
Of the FPU arithmetic operations, FDIV and FSQRT use the FPU arithmetic operation pipeline
and FPU division/square root extraction pipeline.
See section 8.9, Pipeline Operations for Each Instruction, for details.
The CPU pipeline stages are described in detail below.
• IF: Instruction fetch
An instruction is fetched from memory in which the program is stored.
• ID: Instruction decoding
The fetched instruction is decoded.
• EX: Instruction execution
A data operation or address calculation is performed in accordance with the result of decoding.
• MA: Memory access
A memory data access is performed.
Generated by an instruction accompanying a memory access or an instruction that performs
data exchange between the CPU and FPU.
• mm: Multiplier access
A multiplier access is performed.
Generated by an instruction accompanying a memory access or an instruction that loads data
from the CPU to the FPU.
• WB: Write-back
The result (data) accessed by a memory access or multiplier access is returned to the register.
The FPU pipeline stages are described in detail below. CPU and FPU pipelines share the first-
stage instruction fetch (IF).
• DF: FPU decoding
The fetched instruction is decoded.
• E1: FPU execution stage 1
A floating-point operation is initialized.
• E2: FPU execution stage 2
The floating-point operation is executed.
Rev. 3.00 Jul 08, 2005 page 336 of 484
REJ09B0051-0300