SH-2A Datasheet, PDF (318/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.5.12
FMOV
Floating-Point
Transfer
Floating-point MOVe
Floating-Point Instruction
No. SZ Format
Abstract
Code
Cycle
1. 0 FMOV FRm,FRn
2. 1 FMOV DRm,DRn
FRm → FRn
DRm → DRn
1111nnnnmmmm1100 1
1111nnn0mmm01100 2
3. 0 FMOV.S FRm,@Rn
4. 1 FMOV.D DRm,@Rn
5. 0 FMOV.S @Rm,FRn
FRm → (Rn)
DRm → (Rn)
(Rm) → FRn
1111nnnnmmmm1010 1
1111nnnnmmm01010 2
1111nnnnmmmm1000 1
6. 1 FMOV.D @Rm,DRn
7. 0 FMOV.S @Rm+,FRn
8. 1 FMOV.D @Rm+,DRn
(Rm) → DRn
1111nnn0mmmm1000 2
(Rm) → FRn,Rm+=4 1111nnnnmmmm1001 1
(Rm) → DRn,Rm+=8 1111nnn0mmmm1001 2
9. 0
10. 1
11. 0
FMOV.S FRm,@-Rn
Rn-=4,FRm → (Rn) 1111nnnnmmmm1011 1
FMOV.D DRm,@-Rn
Rn-=8,DRm → (Rn) 1111nnnnmmm01011 2
FMOV.S @(R0,Rm),FRn (R0+Rm) → FRn 1111nnnnmmmm0110 1
12. 1
13. 0
14. 1
FMOV.D @(R0,Rm),DRn (R0+Rm) → DRn
FMOV.S FRm, @(R0,Rn) FRm → (R0+Rn)
FMOV.D DRm, @(R0,Rn) DRm → (R0+Rn)
1111nnn0mmmm0110 2
1111nnnnmmmm0111 1
1111nnnnmmm00111 2
T Bit
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Description
1. This instruction transfers FRm contents to FRn.
2. This instruction transfers DRm contents to DRn.
3. This instruction transfers FRm contents to memory at address indicated by Rn.
4. This instruction transfers DRm contents to memory at address indicated by Rn.
5. This instruction transfers contents of memory at address indicated by Rm to FRn.
6. This instruction transfers contents of memory at address indicated by Rm to DRn.
7. This instruction transfers contents of memory at address indicated by Rm to FRn, and adds 4 to
Rm.
8. This instruction transfers contents of memory at address indicated by Rm to DRn, and adds 8
to Rm.
9. This instruction subtracts 4 from Rn, and transfers FRm contents to memory at address
indicated by resulting Rn value.
10. This instruction subtracts 8 from Rn, and transfers DRm contents to memory at address
indicated by resulting Rn value.
Rev. 3.00 Jul 08, 2005 page 304 of 484
REJ09B0051-0300