SH-2A Datasheet, PDF (353/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
8.2 Slots and Pipeline Flow
The interval during which one stage is executed is called a slot. The following rules apply to a
slot.
(1) Each stage of an instruction (IF, ID, EX, MA, WB, mm, E1, E2, DF, ED, SF, NA) is always
executed in one slot. Two or more stages are never executed in one slot (see figure 8.3). The
ED stage operates without regard to a slot.
X
Instruction 1
Instruction 2
↔ ← → ↔ ↔ ↔ ↔ ↔ ↔ ↔ : Slots
IF ID EX MA WB
IF
ID EX MA WB
Note: ID and EX of instruction 1 are executed in one slot.
Figure 8.3 Impossible Pipeline Flow (1)
(2) The maximum number of different stages of different instructions set in one slot is two in the
case of integer pipelines, and one in the case of other pipelines. Simultaneous pipeline
execution never exceeds this number (see figure 8.4).
Instruction 1
Instruction 2
Instruction 3
IF ID EX
IF ID EX MA WB
IF ID EX
Note: Three ID stages are executed in one slot.
Figure 8.4 Impossible Pipeline Flow (2)
(3) The number of states (number of system clock cycles) S required for execution of one slot is
calculated using the following conditions.
(a) S = (maximum number of states among stages of each instruction contained in one slot)
That is to say, instructions that have other short stages are stalled by the longest stage.
(b) The number of execution states of each stage is as follows:
• IF: Number of memory access clocks for instruction fetch
(As a fetch buffer is provided and instruction fetches are performed beforehand,
pipeline stalling only occurs when a fetched instruction must be decoded
immediately.)
• ID: Always 1 state
• EX: Always 1 state
Rev. 3.00 Jul 08, 2005 page 339 of 484
REJ09B0051-0300