SH-2A Datasheet, PDF (466/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(5) FPSCR Store Instruction (STS)
Instruction Type
STS FPSCR,Rn
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX WB
: CPU pipeline
IF DF EX NA
: FPU pipeline
IF — ID EX ⋅ ⋅ ⋅
: CPU pipeline
IF — DF ⋅ ⋅ ⋅
: FPU pipeline
IF ID EX ⋅ ⋅ ⋅
: CPU pipeline
IF DF ⋅ ⋅ ⋅
: FPU pipeline
Operation
The CPU pipeline ends after four stages – IF, ID, EX, MA, WB – and the FPU pipeline after four
stages – IF, DF, EX, NA.
Contention may occur if an instruction that uses the destination of this instruction is located within
the 3 instructions following this instruction.
Instruction Issuance
This instruction uses the multiplication result read path.
If an FPU arithmetic operation instruction is still performing calculation, this instruction is kept
waiting until that instruction ends.
Parallel Execution Capability
This instruction cannot be executed in parallel with FPU instructions or FPU-related CPU
instructions.
Rev. 3.00 Jul 08, 2005 page 452 of 484
REJ09B0051-0300