SH-2A Datasheet, PDF (404/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
8.9.2 Arithmetic Operation Instructions
(1) Inter-Register Arithmetic Operation Instructions
(Excluding Multiply Instructions and DIVU or DIVS Instructions)
Instruction Types
ADD
ADD
ADDC
ADDV
CMP/EQ
CMP/EQ
CMP/HS
CMP/GE
CMP/HI
CMP/GT
CMP/PZ
CMP/PL
CMP/STR
DIV1
DIV0S
DIV0U
DT
EXTS.B
EXTS.W
EXTU.B
EXTU.W
NEG
NEGC
SUB
SUBC
SUBV
CLIPU.B
CLIPU.W
Rm,Rn
#imm,Rn
Rm,Rn
Rm,Rn
#imm,R0
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rn
Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rn
Rn
Rev. 3.00 Jul 08, 2005 page 390 of 484
REJ09B0051-0300