SH-2A Datasheet, PDF (496/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Appendix A SH-2A/SH2A-FPU Parallel Execution
Classifi- Classifi-
cation of cation of
First
Second
Instruction Instruction
Instruction
MR,MU
MR
RESBANK(BO==1)
EX
MR
BAND.B #imm3,@(disp12,Rn) BANDNOT.B #imm3,@(disp12,Rn) BLD.B
#imm3,@(disp12,Rn)
BLDNOT.B #imm3,@(disp12,Rn) BOR.B
#imm3,@(disp12,Rn) BORNOT.B #imm3,@(disp12,Rn)
BXOR.B #imm3,@(disp12,Rn) LDC.L
@Rm+,SR
RTE
SLEEP
TST.B
#imm,@(R0,GBR)
MU
MR
MAC.W
@Rm+,@Rn+
MAC.L
@Rm+,@Rn+
• The first and last steps of multi-step instructions are executed in parallel.
• FPU instructions follow the SH4 classifications ((1) LS type, (2) FE type, (3) CO type). The new 32-bit FMOV
instructions belong to the (1) LS type.
• As a rule, 32-bit instructions are executed in parallel if the preceding instruction is a multi-step instruction.
They cannot be executed in parallel with the instructions that follow them. However, pairs of memory-Tbit bit-
manipulation instructions are executed in parallel.
• The MOVMU.L and MOVML.L instructions cannot be executed in parallel with the instructions that follow
them.
• Parallel execution of delayed branch instructions and delayed slots is not supported.
Multi-step instructions:
TRAPA, MOVMU.L, MOVML.L, AND.B, OR.B, TST.B, XOR.B, TAS.B, BCLR.B, BSET.B, BST.B, BAND.B,
BANDNOT.B, BLD.B, BLDNOT.B, BOR.B, BORNOT.B, BXOR.B, MUL.L, DMULS.L, DMULU.L, MULR,
DIVU, DIVS, FCMP/EQ DRm,DRn, FCMP/GT DRm,DRn, LDC Rm,SR, STC SR,Rn, LDC.L @Rm+,SR,
STC.L SR,@-Rn, LDBANK, STBANK, RESBANK, FMOV.D, FMOV DRm,DRn, JSR/N @@(disp,TBR),
SLEEP, RTE, MAC.W, MAC.L
32-bit instructions:
MOVI20, MOVI20S, MOV.B @(disp12,Rm),Rn, MOV.W @(disp12,Rm),Rn, MOV.L @(disp12,Rm),Rn,
MOV.B Rm,@(disp12,Rn), MOV.W Rm,@(disp12,Rn), MOV.L Rm,@(disp12,Rn),MOVU.B, MOVU.W,
FMOV.S @(disp12,Rm),FRn, FMOV.D @(disp12,Rm),DRn, FMOV.S FRm,@(disp12,Rn), FMOV.D
DRm,@(disp12,Rn), BCLR.B, BSET.B, BST.B, BAND.B, BANDNOT.B, BLD.B, BLDNOT.B, BOR.B,
BORNOT.B, BXOR.B
32-bit FMOV instructions:
FMOV.S @(disp12,Rm),FRn, FMOV.D @(disp12,Rm),DRn, FMOV.S FRm,@(disp12,Rn), FMOV.D
DRm,@(disp12,Rn),
Memory-Tbit bit-manipulation instructions:
BAND.B, BANDNOT.B, BLD.B, BLDNOT.B, BOR.B, BORNOT.B, BXOR.B
Delayed branch instructions:
BRA, BSR, BRAF, BSRF, JMP, JSR, RTS, RTE, BT/S, BF/S
Rev. 3.00 Jul 08, 2005 page 482 of 484
REJ09B0051-0300