SH-2A Datasheet, PDF (276/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.4.60 SUB
SUBtract binary
Binary Subtraction
Format
SUB Rm,Rn
Abstract
Rn – Rm → Rn
Arithmetic Instruction
Code
Cycle T Bit
0011nnnnmmmm1000 1
—
Description
Subtracts general register Rm data from Rn data, and stores the result in Rn. To subtract
immediate data, use ADD #imm,Rn.
Operation
SUB(long m,long n)
{
R[n]-=R[m];
PC+=2;
}
/* SUB Rm,Rn */
Example:
SUB R0,R1 ; Before execution: R0 = H'00000001, R1 = H'80000000
; After execution: R1 = H'7FFFFFFF
Rev. 3.00 Jul 08, 2005 page 262 of 484
REJ09B0051-0300