SH-2A Datasheet, PDF (164/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.3.33 SHAD
SHift Arithmetic Dynamically
Dynamic Arithmetic Shift
Shift Instruction
Format
SHAD Rm, Rn
Abstract
When Rm ≥ 0, Rn<<Rm → Rn
When Rm < 0, Rn>>|Rm| → [MSB → Rn]
Code
0100nnnnmmmm1100
Cycle
1
T Bit
―
Description
Shifts the contents of general register Rn arithmetically. General register Rm specifies the shift
direction and number of bits to be shifted.
A left shift is performed when the Rm register value is positive, and a right shift when negative.
In a right shift, the MSB is added at the upper end.
The number of bits to be shifted is specified by the lower 5 bits (bits 4 to 0) of register Rm. If the
value is negative (MSB = 1), the Rm register value is expressed as a two's complement.
Therefore, the shift amount in a right shift is the value obtained by adding 1 to the inverse of the
lower 5 bits of register Rm. The shift amount is 0 to 31 in a left shift, and 1 to 32 in a right shift.
Rm 0
MSB
LSB
Rm 0
MSB
0
LSB
MSB
Rev. 3.00 Jul 08, 2005 page 150 of 484
REJ09B0051-0300