SH-2A Datasheet, PDF (56/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 4 Instruction Features
Table 4.8 Instruction Formats
Instruction Formats
0 format
15
0
xxxx xxxx xxxx xxxx
n format
15
0
xxxx nnnn xxxx xxxx
m format
15
xxxx mmmm xxxx
0
xxxx
Source
Operand
―
Destination
Operand
―
Example
NOP
―
Control register
or system
register
R0 (register
direct)
Control register
or system
register
mmmm:
Register direct
R15 (register
indirect with
post-increment)
R0 (register
direct)
mmmm:
Register direct
mmmm:
Register indirect
with post-
increment
mmmm:
Register indirect
mmmm:
Register indirect
with pre-
decrement
mmmm: PC-
relative using
Rm
nnnn: Register
direct
nnnn: Register
direct
nnnn: Register
direct
nnnn: Register
indirect with pre-
decrement
R15 (register
indirect with pre-
decrement)
nnnn: Register
direct
nnnn: Register
indirect with post-
increment
Control register or
system register
Control register or
system register
—
R0 (register direct)
—
MOV T Rn
STS MACH,Rn
DIVU R0, Rn
STC.L SR,@-Rn
MOVMU.L
Rm,@-R15
MOVMU.L
@R15+,Rn
MOV.L R0,@Rn+
LDC Rm,SR
LDC.L @Rm+,SR
JMP @Rm
MOV.L @-Rm, R0
BRAF Rm
Rev. 3.00 Jul 08, 2005 page 42 of 484
REJ09B0051-0300