SH-2A Datasheet, PDF (235/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
Example:
Address
1000
1002
1004
1006
MOV
MOV.W
ADD
TST
1008
100A
100C
100E IMM
1010
1012 NEXT
1014
MOVT
BRA
MOV.L
.data.w
.data.w
JMP
CMP/EQ
1018
.align
.data.l
#H'80,R1
IMM,R2
#–1,R0
R0,R0
R13
NEXT
@(4,PC),R3
H'9ABC
H'1234
@R3
#0,R0
4
H'12345678
; R1 = H'FFFFFF80
; R2 = H'FFFF9ABC, IMM means @(H'08,PC)
;
; ← PC location used for address calculation for the
MOV.W instruction
;
; Delayed branch instruction
; R3 = H'12345678
;
;
; Branch destination of the BRA instruction
; ← PC location used for address calculation for the
MOV.L instruction
;
;
Rev. 3.00 Jul 08, 2005 page 221 of 484
REJ09B0051-0300