SH-2A Datasheet, PDF (78/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 5 Instruction Set
5.1.6 System Control Instructions
Table 5.8 System Control Instructions
Instruction
CLRT
CLRMAC
LDBANK @Rm, R0
LDC
Rm, SR
LDC
Rm, TBR
LDC
Rm, GBR
LDC
Rm, VBR
LDC.L @Rm+, SR
LDC.L @Rm+, GBR
LDC.L @Rm+, VBR
LDS
Rm, MACH
LDS
Rm, MACL
LDS
Rm, PR
LDS.L @Rm+, MACH
LDS.L @Rm+, MACL
LDS.L @Rm+, PR
NOP
RESBANK
RTE
SETT
SLEEP
STBANK R0, @Rn
STC
STC
STC
STC
STC.L
STC.L
STC.L
SR, Rn
TBR, Rn
GBR, Rn
VBR, Rn
SR, @- Rn
GBR, @- Rn
VBR, @- Rn
Code
Operation
0000000000001000 0 → T
0000000000101000 0 → MACH, MACL
0100mmmm11100101 (Specified register bank entry)
→ R0
0100mmmm00001110 Rm → SR
0100mmmm01001010 Rm → TBR
0100mmmm00011110 Rm → GBR
0100mmmm00101110 Rm → VBR
0100mmmm00000111 (Rm) → SR, Rm + 4 → Rm
0100mmmm00010111 (Rm) → GBR, Rm + 4 → Rm
0100mmmm00100111 (Rm) → VBR, Rm + 4 → Rm
0100mmmm00001010 Rm → MACH
0100mmmm00011010 Rm → MACL
0100mmmm00101010 Rm → PR
0100mmmm00000110 (Rm) → MACH, Rm + 4 → Rm
0100mmmm00010110 (Rm) → MACL, Rm + 4 → Rm
0100mmmm00100110 (Rm) → PR, Rm + 4 → Rm
0000000000001001 No operation
0000000001011011 Bank → R0 to R14, GBR,
MACH, MACL, PR
0000000000101011 Delayed branch, stack area →
PC/SR
0000000000011000 1 → T
0000000000011011 Sleep
0100nnnn11100001 R0 → (specified register bank
entry)
0000nnnn00000010 SR → Rn
0000nnnn01001010 TBR → Rn
0000nnnn00010010 GBR → Rn
0000nnnn00100010 VBR → Rn
0100nnnn00000011 Rn - 4 → Rn, SR → (Rn)
0100nnnn00010011 Rn - 4 → Rn, GBR → (Rn)
0100nnnn00100011 Rn - 4 → Rn, VBR → (Rn)
Cycles
1
1
6
3
1
1
1
5
1
1
1
1
1
1
1
1
1
9^*
6
1
5
7
2
1
1
1
2
1
1
Compatibility
T Bit
New
SH2E
SH4
SH-2A/
SH2A-
FPU
0 Yes Yes
― Yes Yes
―
Yes
LSB Yes Yes
―
Yes
― Yes Yes
― Yes Yes
LSB Yes Yes
― Yes Yes
― Yes Yes
― Yes Yes
― Yes Yes
― Yes Yes
― Yes Yes
― Yes Yes
― Yes Yes
― Yes Yes
―
Yes
― Yes Yes
1 Yes Yes
― Yes Yes
―
Yes
― Yes Yes
―
Yes
― Yes Yes
― Yes Yes
― Yes Yes
― Yes Yes
― Yes Yes
Rev. 3.00 Jul 08, 2005 page 64 of 484
REJ09B0051-0300