SH-2A Datasheet, PDF (265/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.4.53
SHLL
One-Bit Left
Logical Shift
SHift Logical Left
Section 6 Instruction Descriptions
Shift Instruction
Format
SHLL Rn
Abstract
T ← Rn ← 0
Code
0100nnnn00000000
Cycle
1
T Bit
MSB
Description
Logically shifts the contents of general register Rn to the left by one bit, and stores the result in
Rn. The bit that is shifted out of the operand is transferred to the T bit (figure 6.9).
SHLL
MSB
T
LSB
0
Figure 6.9 Shift Logical Left
Operation
SHLL(long n) /* SHLL Rn (Same as SHAL) */
{
if ((R[n]&0x80000000)==0) T=0;
else T=1;
R[n]<<=1;
PC+=2;
}
Examples:
SHLL R0
; Before execution: R0 = H'80000001, T = 0
; After execution: R0 = H'00000002, T = 1
Rev. 3.00 Jul 08, 2005 page 251 of 484
REJ09B0051-0300