SH-2A Datasheet, PDF (316/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
FMAC Special Cases
FRn FR0
FRm
+Norm –Norm +0
–0 +INF –INF qNaN
Norm Norm MAC
INF
0
Invalid
INF INF
Invalid
INF
+0 Norm MAC
0
+0 Invalid
INF INF
Invalid
INF
–0 +Norm MAC
+0
–0 +INF –INF
–Norm
–0
+0 –INF +INF
+0
+0
–0
+0
–0 Invalid
–0
–0
+0
–0
+0
INF INF
Invalid
INF
+INF +Norm +INF
Invalid
–Norm
+INF
0
Invalid
+INF
Invalid
+INF
–INF Invalid +INF
+INF
–INF +Norm –INF
–INF
–Norm
0
+INF Invalid
Invalid
–INF
–INF –INF
–INF Invalid
qNaN
0
Invalid
INF
Invalid
Norm
!sNaN qNaN
qNaN
All types sNaN
SNaN all types
Note: When DN = 1, the value of a denormalized number is treated as 0.
sNaN
Invalid
Rev. 3.00 Jul 08, 2005 page 302 of 484
REJ09B0051-0300