SH-2A Datasheet, PDF (310/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.5.10
FLOAT
Floating-point
convert from integer
Integer to Floating-Point
Conversion
Floating-Point Instruction
PR Format
Abstract
0 FLOAT FPUL,FRn (float)FPUL → FRn
1 FLOAT FPUL,DRn (double)FPUL → DRn
Code
Cycle
1111nnnn00101101 1
1111nnn000101101 2
T Bit
—
—
Description
When FPSCR.PR = 0: Taking the contents of FPUL as a 32-bit integer, converts this integer to a
single-precision floating-point number and stores the result in FRn.
When FPSCR.PR = 1: Taking the contents of FPUL as a 32-bit integer, converts this integer to a
double-precision floating-point number and stores the result in DRn.
When FPSCR.enable.I = 1, and FPSCR.PR = 0, an FPU exception trap is generated regardless of
whether or not an exception has occurred. When an exception occurs, correct exception
information is reflected in FPSCR.cause and FPSCR.flag, and FRn or DRn is not updated.
Appropriate processing should therefore be performed by software.
Rev. 3.00 Jul 08, 2005 page 296 of 484
REJ09B0051-0300