SH-2A Datasheet, PDF (251/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.4.42 NOT
Bit Inversion
NOT-logical complement
Section 6 Instruction Descriptions
Logical Instruction
Format
NOT Rm,Rn
Abstract
~Rm → Rn
Code
0110nnnnmmmm0111
Cycle
1
T Bit
—
Description
Takes the one’s complement of general register Rm data, and stores the result in Rn. This
effectively inverts each bit of Rm data and stores the result in Rn.
Operation
NOT(long m,long n)
{
R[n]=~R[m];
PC+=2;
}
/* NOT Rm,Rn */
Example:
NOT R0,R1 ; Before execution: R0 = H'AAAAAAAA
; After execution: R1 = H'55555555
Rev. 3.00 Jul 08, 2005 page 237 of 484
REJ09B0051-0300