SH-2A Datasheet, PDF (79/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 5 Instruction Set
Compatibility
Instruction
Code
Operation
Cycles
T Bit
SH2E
SH4
New
SH-2A/
SH2A-
FPU
STS
MACH, Rn
0000nnnn00001010 MACH → Rn
1
― Yes Yes
STS
MACL, Rn
0000nnnn00011010 MACL → Rn
1
― Yes Yes
STS
PR, Rn
0000nnnn00101010 PR → Rn
1
― Yes Yes
STS.L MACH, @-Rn 0100nnnn00000010 Rn - 4 → Rn, MACH → (Rn)
1
― Yes Yes
STS.L MACL, @-Rn 0100nnnn00010010 Rn - 4 → Rn, MACL → (Rn)
1
― Yes Yes
STS.L PR, @-Rn
0100nnnn00100010 Rn - 4 → Rn, PR → (Rn)
1
― Yes Yes
TRAPA #imm
11000011iiiiiiii PC/SR → stack area, (imm × 4
5
+ VBR) → PC
― Yes Yes
Notes: The execution cycles shown in the table are minimums. The actual number of cycles may be increased when (1)
contention occurs between instruction fetches and data access, or (2) when the destination register of the load
instruction (memory → register) and the register used by the next instruction are the same.
* In the event of bank overflow, the number of states is 19.
Rev. 3.00 Jul 08, 2005 page 65 of 484
REJ09B0051-0300