SH-2A Datasheet, PDF (264/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.4.52
SHAR
One-Bit Right
Arithmetic Shift
SHift Arithmetic Right
Shift Instruction
Format
SHAR Rn
Abstract
MSB → Rn → T
Code
0100nnnn00100001
Cycle
1
T Bit
LSB
Description
Arithmetically shifts the contents of general register Rn to the right by one bit, and stores the
result in Rn. The bit that is shifted out of the operand is transferred to the T bit (figure 6.8).
SHAR
MSB
LSB
T
Figure 6.8 Shift Arithmetic Right
Operation
SHAR(long n) /* SHAR Rn */
{
long temp;
if ((R[n]&0x00000001)==0) T=0;
else T=1;
if ((R[n]&0x80000000)==0) temp=0;
else temp=1;
R[n]>>=1;
if (temp==1) R[n]|=0x80000000;
else R[n]&=0x7FFFFFFF;
PC+=2;
}
Example:
SHAR R0
; Before execution: R0 = H'80000001, T = 0
; After execution: R0 = H'C0000000, T = 1
Rev. 3.00 Jul 08, 2005 page 250 of 484
REJ09B0051-0300