SH-2A Datasheet, PDF (357/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
Instructions that transfer data from the FPU to the CPU do not conflict with memory access
instructions (figure 8.10). In addition, instructions that transfer data from the CPU to the FPU do
not conflict with memory access instructions (figure 8.11).
STS FPUL,R0
MOV.L R1,@R3
IF ID EX WB
: CPU pipeline
IF DF EX NA SF
: FPU pipeline
IF ID EX MA WB WB : CPU pipeline
Note: No contention between STS instruction and memory access instruction
Figure 8.10 Example of Contention between STS and Memory Access
LDS R0,FPUL
MOV.L @R1+,R3
IF ID EX
IF DF EX NA SF
IF ID EX MA WB
: CPU pipeline
: FPU pipeline
: CPU pipeline
Note: No contention between LDS instruction and memory read instruction
Figure 8.11 Example of LDS Instruction and Memory Read Instruction
(2) When the preceding instruction and succeeding instruction are both instructions that use the
multiplier (figure 8.12).
With the multiplier, contention also occurs when a previously issued instruction is locked
(figure 8.13).
In addition, instructions that read MACH or MACL, MULR instructions, and instructions that
transfer the value of FPUL or FPSCR to the CPU cause contention because they share the read
bus (figure 8.14).
MULS.W R2,R1
MULR R0,R3
IF ID mm mm
IF — ID mm mm mm WB
Figure 8.12 Example of Multiplier Contention
Multiplier locked
LDS.L @R1+, MACH
MULR R0,R3
↔
IF ID EX MA WB
IF — — ID mm mm mm WA
Figure 8.13 Example of Contention Due to Previously Issued Instruction
Rev. 3.00 Jul 08, 2005 page 343 of 484
REJ09B0051-0300