SH-2A Datasheet, PDF (278/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.4.62
SUBV
SUBtract with (V flag)
underflow check
Binary Subtraction
with Underflow Check
Arithmetic Instruction
Format
SUBV Rm,Rn
Abstract
Code
Cycle T Bit
Rn – Rm → Rn, underflow → T 0011nnnnmmmm1011 1
Underflow
Description
Subtracts Rm data from general register Rn data, and stores the result in Rn. If an underflow
occurs, the T bit is set to 1.
Operation
SUBV(long m,long n) /* SUBV Rm,Rn */
{
long dest,src,ans;
if ((long)R[n]>=0) dest=0;
else dest=1;
if ((long)R[m]>=0) src=0;
else src=1;
src+=dest;
R[n]-=R[m];
if ((long)R[n]>=0) ans=0;
else ans=1;
ans+=dest;
if (src==1) {
if (ans==1) T=1;
else T=0;
}
else T=0;
PC+=2;
}
Rev. 3.00 Jul 08, 2005 page 264 of 484
REJ09B0051-0300