SH-2A Datasheet, PDF (330/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.5.18 FSUB
Floating-Point
Subtraction
Floating-point
SUBtract
PR Format
Abstract
0
FSUB FRm,FRn FRn-FRm → FRn
1
FSUB DRm,DRn DRn-DRm → DRn
Floating-Point Instruction
Code
Cycle
1111nnnnmmmm0001 1
1111nnn0mmm00001 6
T Bit
—
Description
When FPSCR.PR = 0: Arithmetically subtracts the single-precision floating-point number in FRm
from the single-precision floating-point number in FRn, and stores the result in FRn.
When FPSCR.PR = 1: Arithmetically subtracts the double-precision floating-point number in
DRm from the double-precision floating-point number in DRn, and stores the result in DRn.
When FPSCR.enable.O/U/I is set, an FPU exception trap is generated regardless of whether or not
an exception has occurred. When an exception occurs, correct exception information is reflected in
FPSCR.cause and FPSCR.flag, and FRn or DRn is not updated. Appropriate processing should
therefore be performed by software.
Operation
void FSUB (int m,n)
{
pc += 2;
clear_cause();
if((data_type_of(m) == sNaN) ||
(data_type_of(n) == sNaN)) invalid(n);
else if((data_type_of(m) == qNaN) ||
(data_type_of(n) == qNaN)) qnan(n);
else switch (data_type_of(m)){
case NORM: switch (data_type_of(n)){
case NORM: normal_faddsub(m,n,SUB); break;
case PZERO:
case NZERO: register_copy(m,n); FR[n] = -FR[n];break;
default:
break;
Rev. 3.00 Jul 08, 2005 page 316 of 484
REJ09B0051-0300