SH-2A Datasheet, PDF (370/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(3) At the end of an FDIV or FSQRT instruction, operation write-back occurs. The E1 stage is
used again here, and therefore if an instruction requests E1 stage operation from just this point
onward, the subsequent instruction is kept waiting until the FDIV or FSQRT instruction
finishes using the E1 stage (figure 8.44).
(4) An FDIV or FSQRT instruction immediately following an FDIV or FSQRT instruction cannot
enter the ED stage while the preceding FDIV or FSQRT instruction is using the ED stage.
Instruction 1
IF
(single-precision)
(FDIV FR6,FR7)
Instruction 2
(single-precision)
(FADD FR8,FR10)
DF E1 ED ED ED ED ED ED ED ED E1 E2 SF
IF DF E1 E2 SF
Figure 8.43 Example 1 of E1 Stage Contention Due to FDIV
Instruction 1
IF
(single-precision)
(FDIV FR6,FR7)
Other instruction
Instruction 2
(single-precision)
(FADD FR8,FR10)
Instruction 3
(single-precision)
(FADD FR9,FR11)
DF E1 ED ED ED ED ED ED ED ED E1 E2 SF
:
IF DF E1 E2 SF
IF — DF E1 E2 SF
Figure 8.44 Example 2 of E1 Stage Contention Due to FDIV
If a write was performed by a previous instruction on a register used as a source register by a
double-precision arithmetic operation instruction, and the latency of the previous instruction is 2
cycles or less, the latency of those instructions will be 2 (figure 8.45).
Rev. 3.00 Jul 08, 2005 page 356 of 484
REJ09B0051-0300