SH-2A Datasheet, PDF (89/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.2 Format of Instruction Descriptions
Format of this Section: The format used for describing instructions is as shown below.
Instruction Name
Instruction Function
Instruction Function (Explanation
of Instruction Name)
Instruction Type
Instruction Set
Compatibility
Format
Shown in assembler
input format. imm and
disp are numeric
values, expressions,
or symbols.
Abstract
Summarizes the
operation.
Code
Shown in MSB ↔
LSB order.
Cycles
Value in case
of no-wait
operation.
T Bit
Shows the
value of the T
bit after
execution of
the instruction.
Description
Describes the operation of the instruction.
Notes
Mentions points requiring particular attention when using the instruction.
Operation
Shows the operation of the instruction in C. Provided as a reference to explain the operation of the
instruction. The use of the following resources is assumed here.
unsigned char
Read_Byte (unsigned long Addr);
unsigned short Read_Word (unsigned long Addr);
unsigned int
Read_Int (unsigned long Addr);
unsigned long
Read_Long (unsigned long Addr);
unsigned double Read_Quad (unsigned long Addr);
The size of address Addr is returned. A word read from other than a 2n address or a longword read from
other than a 4n address will be detected as an address error.
unsigned long
Read_Bank_Long (unsigned long Addr);
The contents of the register bank entry indicated by the contents of address Addr are returned.
Rev. 3.00 Jul 08, 2005 page 75 of 484
REJ09B0051-0300