SH-2A Datasheet, PDF (339/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 Register Banks
Section 7 Register Banks
7.1 Overview
The SH-2A/SH2A-FPU has on-chip register banks to provide high-speed register save and retrieve
performance during interrupt processing. The configuration of the register banks is shown in
figure 7.1.
Registers
General
R0
registers
R1
Control
registers
R14
R15
SR
GBR
VBR
TBR
System
registers
MACH
MACL
PR
PC
Register banks
R0
R1
Interrupt generated
(save)
R14
GBR
RESBANK instruction
(retrieve)
MACH
MACL
PR
VTO
Bank 0
Bank 1
.....
Bank
N-1
Bank control registers (interrupt controller)
Bank control register
IBCR
Bank number register
IBNR
Notes:
VTO
: Banked register
: Interrupt vector table
address offset
Figure 7.1 Overview of Register Bank Configuration
Rev. 3.00 Jul 08, 2005 page 325 of 484
REJ09B0051-0300