SH-2A Datasheet, PDF (24/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 2 Programming Model
RM: Rounding Mode
RM = 00: Round to Nearest
RM = 01: Round to Zero
RM = 10: Reserved
RM = 11: Reserved
Bits 21, 23 to 31: Reserved
Note: The SH-2A does not generate an FPU error.
2.2.6 Register Banks
For the nineteen 32-bit registers comprising general registers R0 to R14, control register GBR, and
system registers MACH, MACL, and PR, high-speed register saving and restoration can be carried
out using a register bank. Saving to the bank is performed automatically after the CPU accepts an
interrupt that uses a register bank. Restoration from the bank is executed by issuing a RESBANK
instruction in an interrupt service routine.
For details, refer to section 7, Register Banks.
2.2.7 Register Initial Values
Table 2.1 Initial Values of Registers
Classification
General registers
Control registers
Register
R0–R14
R15(SP)
SR
System registers
GBR, TBR
VBR
MACH, MACL, PR
PC
Floating-point registers
Floating-point system registers
FRR0–FRR15
FPUL
FPSCR
Initial Value
Undefined
SP value in the program address table
Bits I3–I0 are 1111 (H'F), BO, CS are 0,
reserved bits are 0, and other bits are
undefined
Undefined
H'00000000
Undefined
Value of the program counter in the vector
address table
Undefined
Undefined
H'00040001
Rev. 3.00 Jul 08, 2005 page 10 of 484
REJ09B0051-0300