SH-2A Datasheet, PDF (20/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 2 Programming Model
(4) Jump Table Base Register, TBR (32-bit, initial value = undefined)
TBR is referenced as the start address of a function table located in memory in a JSR/N
@@(disp8,TBR) table referencing subroutine call instruction.
2.2.3 System Registers
System registers consist of four 32-bit registers: high and low multiply and accumulate registers
(MACH and MACL), the procedure register (PR), and the program counter (PC). The multiply
and accumulate registers store the results of multiply and multiply and accumulate operations. The
procedure register stores the return address from the subroutine procedure. The program counter
indicates the address of the program executing and controls the flow of the processing.
31
MACH
MACL
31
PR
31
PC
0 _{Multiply and accumulate}
register high (MACH)
Multiply and accumulate
register low (MACL)
0 _{Procedure register (PR):}
Stores the return address for
a subroutine procedure.
0 _{Program counter (PC):}
Indicates the fourth byte after
the current instruction.
(1) Multiply and Accumulate Register High, MACH (32-bit, initial value = undefined)
Multiply and Accumulate Register Low, MACL (32-bit, initial value = undefined)
MACH/MACL is used as the addition value in a MAC instruction, and to store the operation result
of a MAC or MUL instruction.
(2) Procedure Register, PR (32-bit, initial value = undefined)
PR stores the return address of a subroutine call using a BSR, BSRF, or JSR instruction, and is
referenced by a subroutine return instruction (RTS).
(3) Program Counter, PC (32-bit, initial value = value of PC in vector table)
The PC indicates the address of the instruction being executed.
Rev. 3.00 Jul 08, 2005 page 6 of 484
REJ09B0051-0300