HD64570 Datasheet, PDF (99/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

4.2 Registers
The SCA has nine registers for interrupt control. These registers can be accessed by read and write
instructions from the MPU.
4.2.1 Interrupt Vector Register (IVR)
The interrupt vector register stores the vector address output to the MPU in an interrupt
acknowledge cycle.
7
6
5
4
3
2
1
0
Bit name
IVR7 IVR6 IVR5 IVR4 IVR3 IVR2 IVR1 IVR0
Read/Write
Initial value
R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
Fixed vector address
Any desired vector address can be set. Vector output will be detailed in section 4.3, Vector Output.
4.2.2 Interrupt Modified Vector Register (IMVR)
The interrupt modified vector register stores a modifiable vector address output to the MPU in an
interrupt acknowledge cycle.
The register consists of eight bits. The six low-order bits hold a hardware-generated code
identifying the interrupt source. If multiple interrupt sources are active simultaneously, IMVR
holds the code of the source with the highest priority. Any desired value can be set in bits 7 and 6
(IMVR7, IMVR6).
Rev. 0, 07/98, page 83 of 453