HD64570 Datasheet, PDF (441/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Register
MSCI (Channel 1)
MSCI RX Clock Source
Register Channel 1:
RXS Channel 1
Address
CPU CPU
Mode Mode
0, 1 2, 3 Remarks
56H 57H
7
Async
—
Byte sync
Bit sync HDLC
Read/Write
—
Initial value
0
6
5
4
3
2
1
0
RXCS2 RXCS1 RXCS0 RXBR3 RXBR2 RXBR1RXBR0
R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
MSCI TX Clock Source
57H 56H
Register Channel 1: TXS
Channel 1
Receive clock source
000: RXC line input
010: RXC line input (noise suppression)
100: Internal baud rate generator (BRG) output
110: ADPLL output
(BRG output for ADPLL operating clock)
111: ADPLL output
(RXC line input for ADPLL operating clock)
Others: Reserved
Receiver baud rate
• Clock division ratio
0000: 1/1
0001: 1/2
0010: 1/4
0011: 1/8
0100: 1/16
0101: 1/32
0110: 1/64
0111: 1/128
1000: 1/256
1001: 1/512
Others: Reserved
7
Async
—
Byte sync
Bit sync HDLC
Read/Write
—
Initial value
0
6
5
4
3
2
1
0
TXCS2 TXCS1 TXCS0 TXBR3 TXBR2 TXBR1 TXBR0
R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
MSCI TX Ready Control
Register 0 Channel 1:
TRC0 Channel 1
58H 59H
Transmit clock source
000: TXC line input
100: Internal baud rate generator (BRG) output
110: Receive clock
Others: Reserved
Transmitter baud rate
• Clock division ratio
0000: 1/1
0001: 1/2
0010: 1/4
0011: 1/8
0100: 1/16
0101: 1/32
0110: 1/64
0111: 1/128
1000: 1/256
1001: 1/512
Others: Reserved
7
6
5
4
3
2
1
0
Async
— — — TRC04 TRC03 TRC02 TRC01 TRC00
Byte sync
Bit sync HDLC
Read/Write
—
—
— R/W R/W R/W R/W R/W
Initial value
0
0
0
0
0
0
0
0
TX ready control 0
Rev. 0, 07/98, page 425 of 453