HD64570 Datasheet, PDF (163/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

TXENBL = 1:Indicates that the transmitter is enabled
Bit 0 (RXENBL: RX Enable): Indicates whether the receiver is enabled or disabled. Receiver
enable/disable selection is performed by a command. This is a read-only bit, and writing to it has
no effect.
• Asynchronous/Byte synchronous/Bit synchronous mode
RXENBL = 0:
Indicates that the receiver is disabled
RXENBL = 1:
Indicates that the receiver is enabled
5.2.13 MSCI Frame Status Register (FST)
The frame status register (FST) (figure 5.16) holds the status of the last frame received in bit
synchronous mode.
The reset descriptions of this register's bits are as follows:
• When 1 is written to a particular bit position, that bit is reset
• All bits are reset by an RX or channel reset command
• All bits are reset in system stop mode
When the EOMF bit is set to 1, an MPU interrupt request is generated (if enabled). The other bits
do not generate interrupts.
Async
7
6
5
4
3
2
1
0
—* —* —* —* —* —* —* —*
Byte sync
Bit sync HDLC EOMF SHRTF ABTF RBITF OVRNFCRCEF
Read/Write R/W R/W R/W R/W R/W R/W — —
Initial value
0
0
0
0
0
0
0
0
Frame status at receive completion
Note: The bits marked with * are reserved. These bits always read 0 and can be
set to 0 or 1.
When data with EOM bit = 1 (last character of the frame) is read from the receive buffer, the
character status, which is reflected by bits 7−2 of status register 2 (ST2), is transferred and set in
FST. This clears all bits of ST2 (figure 5.5). The definition of each bit of FST is the same as that
of the corresponding bit of ST2. See section 5.2.11, MSCI Status Register 2 (ST2).
Rev. 0, 07/98, page 147 of 453