HD64570 Datasheet, PDF (46/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Memory
DMAC
SCA
MSCI
DMA Request
RXRDY active
When the number of bytes of data in
RX FIFO has risen to the number set in
MSCI RX ready control register (RRC) +
1 or greater, and RX FIFO has not
subsequently become empty
Get bus
Access memory
1.
2.
Put
AS
address
active
on
bus
(A₀
to
A₂₃)
Store data
1. Decode address
2. Write data
3. WAIT inactive
Data valid
WR active
Send data
Put data on bus
End of transfer
AS and WR inactive
End of cycle
WAIT active
End of cycle
If RX FIFO is empty after
this transfer, negate the
DMA request
Relinquish bus
Or start next cycle
Figure 1.18 Receive DMA Operation (CPU mode 1)
Rev. 0, 07/98, page 30 of 453