HD64570 Datasheet, PDF (108/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

4.2.7 Interrupt Enable Register 0 (IER0)
The interrupt enable register 0 enables or disables interrupt requests indicated in interrupt status
register 0 (ISR0). All IER0 bits are cleared to 0 at a reset.
7
6
5
4
3
2
1
0
Bit name TXINT1ERXINT1ETXRDY1REXRDY1ETXINT0ERXINT0ETXRDY0REXRDY0E
Read/Write
Initial value
R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
MSCI channel 1
TXINT enable
0: Disabled
1: Enabled
MSCI channel 1
RXINT enable
0: Disabled
1: Enabled
MSCI channel 1
TXRDY enable
0: Disabled
1: Enabled
MSCI channel 1
RXRDY enable
0: Disabled
1: Enabled
Note: Initial values are the values after a hardware reset.
MSCI channel 0
RXRDY enable
0: Disabled
1: Enabled
MSCI channel 0
TXRDY enable
0: Disabled
1: Enabled
MSCI channel 0
RXINT enable
0: Disabled
1: Enabled
MSCI channel 0
TXINT enable
0: Disabled
1: Enabled
Bit 7 (TXINT1E: MSCI Channel 1 TXINT Enable):
TXINT1E = 0: The MSCI channel 1 TXINT interrupt is disabled.
TXINT1E = 1: The MSCI channel 1 TXINT interrupt is enabled.
Rev. 0, 07/98, page 92 of 453