HD64570 Datasheet, PDF (98/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 4.1 lists the interrupts in priority order and names of their sources.
Table 4.1 Interrupt Priority and Interrupt Sources
Module
Interrupt Name
Priority
Interrupt Source
MSCI0
RXRDY0
High
Receive buffer ready
(channel 0)
MSCI0
TXRDY0
Transmit buffer ready
(channel 0)
MSCI0
RXINT0
Receive status
(channel 0)
MSCI0
TXINT0
Transmit status
(channel 0)
MSCI1
RXRDY1
Receive buffer ready
(channel 1)
MSCI1
TXRDY1
Transmit buffer ready
(channel 1)
MSCI1
RXINT1
Receive status
(channel 1)
MSCI1
TXINT1
Transmit status
(channel 1)
DMAC0
DMIA0
Error interrupt
(channel 0)
DMAC0
DMIB0
Normal end interrupt
(channel 0)
DMAC1
DMIA1
Error interrupt
(channel 1)
DMAC1
DMIB1
Normal end interrupt
(channel 1)
DMAC2
DMIA2
Error interrupt
(channel 2)
DMAC2
DMIB2
Normal end interrupt
(channel 2)
DMAC3
DMIA3
Error interrupt
(channel 3)
DMAC3
DMIB3
Normal end interrupt
(channel 3)
Timer 0
T0IRQ
Count match
(channel 0)
Timer 1
T1IRQ
Count match
(channel 1)
Timer 2
T2IRQ
Count match
(channel 2)
Timer 3
T3IRQ
Low
Count match
(channel 3)
Note: The MSCI and DMAC priorities can be interchanged by setting a bit in the interrupt control
register (ITCR). For details, see section 4.2.3, Interrupt Control Register, and section 4.2.2,
Interrupt Modified Vector Register.
Interrupt requests are generated by status bits set in interrupt status registers 0, 1, and 2 (ISR0,
ISR1, ISR2). If a requested interrupt is enabled by the corresponding bit in interrupt enable
register 0, 1, or 2 (IER0, IER1, IER2), the request is sent to the MPU.
See sections 4.2.4 to 4.2.9 for details of interrupt status registers 0 to 2 and interrupt enable
registers 0 to 2.
Rev. 0, 07/98, page 82 of 453