HD64570 Datasheet, PDF (189/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Bits 7−2: Indicate the status of the data in the second stage of the receive buffer. These bits are
arranged in the same way as bits 7−2 of status register 2 (ST2). When data is in the second stage
of the receive buffer, the status of the second stage of the status FIFO is set to these bits. The
status is activated when the TX/RX buffer register (TRB) is ready to be read. When data is read
from TRB, the status of the data is cleared and replaced by the status of the following data. When
there is no subsequent data, the status remains cleared.
Bit 1: Reserved. This bit always reads 0 and must be set to 0.
Bit 0 (CDE1: Current Data 1): Indicates that data is in the second stage of the receive buffer.
This bit is set to 1 when TRB is ready to be read, and is cleared when data has been read with no
subsequent data.
CDE1 = 0: Indicates that no data is in the second stage of the receive buffer
CDE1 = 1: Indicates that data is in the second stage of the receive buffer
This register and current status register 0 (CST0) are used by the MPU for interrupt processing and
receive buffer access. For details, see section 5.2.25, MSCI Current Status Register 0 (CST0).
Rev. 0, 07/98, page 173 of 453