HD64570 Datasheet, PDF (247/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Bit Rate
(bps)
f_CLK (MHz)
9.8304
10
TMC BR CM Deviation (%) TMC BR CM Deviation (%)
38400 2
1
1/64 0.00




19200 2
2
1/64 0.00




9600 2
3
1/64 0.00
65
0
1/16 0.16
4800 2
4
1/64 0.00
65
0
1/32 0.16
2400 2
5
1/64 0.00
65
0
1/64 0.16
1200 2
6
1/64 0.00
65
1
1/64 0.16
600
2
7
1/64 0.00
65
2
1/64 0.16
300
2
8
1/64 0.00
65
3
1/64 0.16
150
2
9
1/64 0.00
65
4
1/64 0.16
110
175 3
1/64 −0.25
89
4
1/64 − 0.25
TMC:
BR:
CM:
Value of the TMC7−TMC0 bits of TMC
Value of the TXBR3−TXBR0 bits of TXS or the RXBR3−RXBR0 bits of RXS
Value of the BRATE1−BRATE0 bits of MD1 (clock mode in asynchronous mode (bit
rate/clock frequency))
Rev. 0, 07/98, page 231 of 453