HD64570 Datasheet, PDF (354/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

MPU
(8086, HD64180 etc.)
Address bus
Data bus
Control bus
Memory
HD64570
(SCA)
TXD0
RXD0
TXD1
RXD1
Circuit
interface
Figure 9.7 System Configuration Incorporating the SCA
Channel 0
Channel 1
9.2.2 Bus Arbitration Block
The SCA BUSREQ (HOLD) signal indicates a bus request, but not bus acquisition. Bus
acquisition is indicated by the BUSY signal. When connecting the SCA to the MPU that uses
BUSREQ and BUSACK to arbitrate the bus:
1. Input the result of ORing the SCA BUSREQ signal with the BUSY signal to the MPU
BUSREQ line.
2. Input the result of ANDing the MPU BUSACK signal with the SCA BUSREQ signal to the
SCA BUSACK line.
This is shown in figure 9.8. Possible bus masters are one MPU and one SCA; no other bus
masters are considered. For more details of bus arbitration for a specific MPU, refer to figure 9.9.
Note that if the SCA BUSREQ and BUSACK signals and the MPU BUSREQ and BUSACK
signals are connected to each other, respectively, malfunction occurs if the SCA BUSREQ signal
is activated after it has been temporarily inactivated for one clock pulse. This is because the SCA,
mistakenly determining that it has acquired the bus because the BUSACK signal is not inactivated,
starts a DMA transfer. At the same time, the MPU, also mistakenly determining that it has
acquired the bus, starts using the bus and inactivates the BUSACK signal. As a result, the SCA
and the MPU use the bus at the same time, causing a malfunction.
To securely inform the HD64180 that the SCA has acquired the bus, connect the OR between the
SCA BUSREQ and BUSY signals to the HD64180 BUSREQ pin. To securely inform the SCA
that the HD64180 has released the bus, also connect the result of ANDing the SCA BUSREQ-
synchronous signal with the HD64180 BUSACK signal to the SCA BUSACK pin. Note that there
are no wait cycles during DMA transfers from the SCA.
Rev. 0, 07/98, page 338 of 453