HD64570 Datasheet, PDF (363/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 10.7 CPU Mode 0 Master Mode Bus Timing
(V_CC = 5 V ± 10%, V_SS = 0 V, Ta = −20 to +75°C unless otherwise specified)
Item
Clock cycle time
Symbol Min Typ Max Unit
t _CLCL
100 
2000 ns
Clock high-level pulse width
Clock low-level pulse width
Clock fall time
Clock rise time
Address delay time
Address set-up time
AS active delay time
RD active delay time
Address hold time
AS inactive delay time
RD inactive delay time
Data read set-up time
Data read hold time
WAIT set-up time
WAIT inactive set-up time
WAIT hold time
Write data floating delay time
WR active delay time
Write data delay time
Write data set-up time
WR inactive delay time
WR pulse width
Write data hold time
AS high-level pulse width
AS low-level pulse width
t _CHCL
40


ns
t _CLCH
40


ns
t _CL2CL1


10
ns
t _CH1CH2


10
ns
t _CLAV


55
ns
t _AVAL
20


ns
t _CHLL


50
ns
t _CLRL


50
ns
t _LLAX
10


ns
t _CLLH


50
ns
t _CLRH


50
ns
t _DVCL
25


ns
t _RDX
0


ns
t _RYLCL
30


ns
t _RYHCH
30


ns
t _CHRYX
30


ns
t _CHDX


60
ns
t _CVCTV


50
ns
t _CLDV


60
ns
t _DVWL
15


ns
t _CVCTX


55
ns
t _WLWH
110 

ns
t _WHDX
10


ns
t _ASWH
70


ns
t _ASWL
80


ns
Timing
Figure 10.5,
figure 10.6
Rev. 0, 07/98, page 347 of 453