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| HD64570 Datasheet, PDF (89/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor | |||
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CPU Mode 1: The SCA latches the address on lines A0 to A7 when CS is driven active low. CS
must remain low throughout the bus cycle. After the bus cycle ends, CS must go high (inactive).
Figure 3.10 shows the slave mode bus timing sequence in CPU mode 1.
⢠Read cycle
If RD is low (active) at the falling clock edge in the T2 state, the SCA outputs the contents of
the register specified by the address on the data bus on the rising clock edge between the T3
and T4 states. RD must remain low until the falling clock edge in the T4 state. When RD goes
high (inactive), the cycle ends: the SCA then drives the WAIT output active high and lets the
data bus float. The read cycle can be extended by delaying the high transition of RD.
⢠Write cycle
If WR is low (active) at the rising clock edge between the T2 and T3 states, the SCA latches the
data on the data bus on the falling clock edge in the T3 state, and stores the data in the register
specified by the address. WR must remain low until the falling clock edge in the T5 state.
When WR is driven high (inactive), the cycle ends: the SCA drives the WAIT output active
high.
CLK
T1 T2
T3
T4
T1
T2 T3
T4 T5
A0 to A 7
CS
Register address
Register address
RD
WR
WAIT
D0 to D7
(Out)
D0 to D7
(In)
Output data
Read cycle SCA âMPU
Input data
Data latch point
Write cycle MPU âSCA
Note: State numbers do not match MPU state numbers.
Figure 3.10 Slave Mode Bus Timing Sequence in CPU Mode 1
CPU Mode 2: The SCA latches the address on lines A1 to A7 when CS and AS are both driven
active low. CS and AS must remain low throughout the bus cycle. After the bus cycle ends, they
must go high (inactive). Figure 3.11 shows the slave mode bus timing sequence in CPU mode 2.
Rev. 0, 07/98, page 73 of 453
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