HD64570 Datasheet, PDF (65/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 2.6 Bus Interface Lines (cont)
Pin Number
Symbol
WAIT
CP-84
81
FP-88
8
Input/
Output
Description
Input/ Wait: Used to extend read and write cycles.
output
CPU mode 0
Master mode
If this line is high at the rising
edge of a T₂ state, a T_W state is
inserted. If the line is still high
at the rising edge of the next
T_W state, another T_W state is
inserted. If this line is low at
the rising edge of a T₂ or TW
state, the next state is a T₃
state.
Slave mode
Output line. This line is driven
high to request the host MPU
to extend the bus cycle.
Reset mode High output.
System stop High output.
mode
CPU modes 1, 2, 3
Master mode
If this line is high at the falling
edge of a T₂ state, a T_W state is
inserted. If the line is still high
at the falling edge of the next
T_W state, another T_W state is
inserted. If this line is low at
the falling edge of a T₂ or T_W
state, the next state is a T₃
state.
Slave mode
Output line. This line is driven
high to request the host MPU
to extend the bus cycle.
Reset mode High output.
System stop High output.
mode
Rev. 0, 07/98, page 49 of 453