HD64570 Datasheet, PDF (319/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Section 7 Timer
7.1 Overview
7.1.1 Functions
The HD64570 incorporates a timer with four identically functioning channels 0, 1, 2, and 3.
This timer has the following functional features:
• 16-bit reloadable data
• Operates on a base clock (BC) (φ clock internally divided by eight)
 Increment intervals in the range of BC/2⁰−BC/2⁷
• Interrupt issued when a counter value matches a specified value
7.1.2 Configuration and Operation
Figure 1.4 shows the timer block diagram.
In this timer, the timer up-counter (TCNT) increments based on the specified clock signal. When
the TCNT value matches the specified value in the timer constant register (TCONR), an interrupt
is generated, if enabled. For details on interrupt timing, see section 7.4, Interrupt. Here, the
TCNT value is cleared to 0000H, and incrementation restarts from 0000H. For details on timer
increment timing, see section 7.3.1, Timer Increment Timing.
7.2 Registers
7.2.1 Timer up-counter (TCNT: TCNTH, TCNTL)
The timer up-counter (TCNT), provided for each of channels 0, 1, 2, and 3, increments based on
the clock signal specified by the ECKS2−ECKS0 bits of the timer expand prescale register
(TEPR). For information regarding clock selection, see section 7.2.4, Timer Expand Prescale
Register (TEPR).
The MPU can read/write TCNT without affecting TCNT operation. When the TCNT value was
changed during incrementing, time t between the start of the TCNT write cycle and the start of
TCNT incrementing is c ≤ t ≤ n × 8 + c − 1, where c is 4, 5, 6, or 5 in CPU mode 0, 1, 2, or 3,
respectively.
The TCNT value is initialized to 0000H after its value matches the value in the timer constant
register (TCONR).
Rev. 0, 07/98, page 303 of 453