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HD64570 Datasheet, PDF (182/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor
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Table 5.9 TRB Write Operation in CPU Mode 0
Read Mode
Word write
Byte write
Accessed Register*2
TRBH
TRBL
TRBH
TRBL
Empty Data Byte Count in Transmit Buffer*1
2 or More Bytes 1 Byte
None
B*3
*4
*4
A*3
*4
*4
A*3
A*3
*4
A*3
A*3
*4
Table 5.10 TRB Write Operation in CPU Mode 1
Read Mode
Byte write
Accessed Register*2
TRBH
TRBL
Empty Data Byte Count in Transmit Buffer*1
2 or More Bytes 1 Byte
None
A*3
A*3
*4
A*3
A*3
*4
Table 5.11 TRB Write Operation in CPU Modes 2, 3
Empty Data Byte Count in Transmit Buffer*1
Read Mode
Accessed Register*2 2 or More Bytes
1 Byte
None
Word write
TRBH
A*3
*4
*4
TRBL
B*3
*4
*4
Byte write
TRBH
A*3
A*3
*4
TRBL
A*3
A*3
*4
Notes: 1. Because the empty data byte count in the transmit buffer is unknown to the user, extra
care must be taken in writing data to the transmit buffer using the MPU. Set the
TRC14−TRC10 bits of TX ready control register 1 (TRC1) to 1EH or less in CPU modes
0, 2, and 3 (1FH in CPU mode 1), and confirm that the TXRDY bit of status register 0
(ST0) is 1 before writing data to the transmit buffer. (Do not write data to the transmit
buffer when the TXRDY bit is 0.) However, this procedure is not necessary in built-in
DMA transfer.
2. TRBH and TRBL are simultaneously accessed in word write mode, and either TRBH or
TRBL is accessed in byte write mode.
3. Empty bytes A and B are arranged in the order as shown in figures 5.9 (a) and (b). The
transmit buffer sends A and B to the serial unit in that order.
4. Data is lost except in built-in DMA transfer. Data in the transmit buffer is not lost, but
writing data to the full buffer does not guarantee subsequent operation.
Rev. 0, 07/98, page 166 of 453
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