HD64570 Datasheet, PDF (242/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

5.6.2 Functions
The MSCI baud rate generator generates clock pulses according to the settings of the TMC7−
TMC0 bits of the time constant register (TMC), the TXBR3−TXBR0 bits of the TX clock source
register (TXS), and the RXBR3−RXBR0 bits of the RX clock source register (RXS).
TMC is an 8-bit register for specifying the value to be loaded into the reload timer in the baud rate
generator. The reload timer is decremented based on the system clock CLK, and outputs a high-
level signal for one clock cycle each time the reload timer value equals 1. Thus, the timer outputs
a high-level signal for one clock cycle each time the number of system clock cycles specified with
the TMC7−TMC0 bits of TMC elapses, as shown in figure 5.44. Zero specified by TMC is
assumed to be 256, and when 1 is specified, the output will be the same as the system clock
frequency.
CLK (CPU modes 1, 2, 3)
TMC7–TMC0 bit values
CLK (CPU mode 0)
Reload timer output
Figure 5.44 Reload Timer Output
The reload timer output is input to the frequency divider. The transmit frequency division ratio is
specified with the TXBR3−TXBR0 bits of TXS and the receive frequency division ratio with the
RXBR3−RXBR0 bits of RXS.
In addition, the TXCS2−TXCS0 bits of TXS and RXCS2−RXCS0 bits of the RXS specify
whether or not to supply the output clock to the MSCI transmitter and receiver, respectively. The
BRG output can be used for the transmit/receive clock or for the ADPLL operating clock. For
details on these specifications, see sections 5.2.4, MSCI Control Register (CTL), 5.2.5, MSCI RX
Clock Source Register (RXS), and 5.2.6, MSCI TX Clock Source Register (TXS).
The relationship between the register set values and the generated clock frequency is given below.
f_BRG =
f_CLK
÷ 2^BR
Rev. 0, 07/98, page 226 of 453