HD64570 Datasheet, PDF (439/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Address
Register
CPU CPU
Mode Mode
0, 1 2, 3 Remarks
MSCI (Channel 1)
MSCI Control Register
51H 50H
Channel 1: CTL Channel 1
7
Async
—
Byte sync
Bit sync HDLC
Read/Write
—
Initial value
0
6
5
4
3
2
1
—
—
— _BRK —
—
UDRNC IDLC — SYNCLD
—
0
RTS
— R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
1
MSCI Synchronous/
52H
Address Register 0
Channel 1: SA0 Channel 1
53H
Idle state control
• Byte/Bit synchronous mode
0: Transmits a mark
1: Transmits an idle pattern
Send break
• Asynchronous
mode
Underrun state control
0: Off
• Byte synchronous mode
1: On (break send)
0: Enters idle state immediately
1: Enters idle state after CRC transmission
• Bit synchronous mode
0: Enters idle state after aborting transmission
1: Enters idle state after FCS and flag transmission
Request to send
0: Sets RTS low
1: Sets RTS high
SYN character
load enable
• Byte synchronous mode
0: Disable
1: Enable
Async
7
6
5
4
3
2
1
0
————————
Byte sync
SA07 SA06 SA05 SA04 SA03 SA02 SA01 SA00
Bit sync HDLC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial/value
1
1
1
1
1
1
1
1
SYN pattern for reception/address field check
• Byte synchronous mode
Mono-sync
Bi-sync
External-sync
SYN pattern for reception
SYN pattern for transmission and reception (bit7–bit0)
Not used
• Bit synchronous mode
No address field checked
HDLC ^{Single address 1}
mode _{Single address 2}
Dual address
Not used
Bit7–bit0 of the secondary station address
Not used
Bit7–bit0 of the secondary station address
Rev. 0, 07/98, page 423 of 453