HD64570 Datasheet, PDF (386/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 10.32 CPU Mode 3 Slave Mode Bus Timing
(V_CC = 5 V ± 10%, V_SS = 0 V, Ta = −40 to +85°C unless otherwise specified)
Item
Symbol Min Typ Max Unit Timing
Address set-up time
t _ADS
30


ns
Address hold time
t _ADH
0


ns
AS set-up time
t _ASS
30


ns
AS hold time
t _ASH
0


ns
CS set-up time
t _CSS
30


ns
CS hold time
t _CSH
0


ns
HDS, LDS active set-up time
t _DSS1
30


ns
HDS, LDS inactive set-up time
t _DSS2
30


ns
HDS, LDS inactive hold time
t _DSH1
10


ns
HDS, LDS active hold time
t _DSH2
0


ns
R/W set-up time
t _RWS
30


ns
R/W hold time 1
t _RWH1
0


ns
R/W hold time 2
t _RWH2
0


ns
WAIT inactive delay time
t _WTD1


50
ns
WAIT active delay time
t _WTD2


50
ns
Read data active delay time
t _DBD1


60
ns
Read data hold time
t _DBD2
10


ns
Read data floating delay time
t _DBZ


60
ns
Write data set-up time
t _DBS
25


ns
Write data hold time
t _DBH
20


ns
Write data WAIT hold time
t _DBWH
0


ns
Note: The CLK timing is the same in this mode and DMA mode. See table 10.9.
Figure 10.4
Rev. 0, 07/98, page 370 of 453